A characteristic of EEPROMs is that they have a finite number of times that they can be erased and programmed. For each time an EEPROM cell is erased and programmed, electrons are tunneled to and from a floating gate of the EEPROM. The floating gate is electrically isolated so it will remain charged indefinitely. After some number of times of erasing and programming, however, the charge will leak away so that the floating gate loses its charge. In the programmed state the floating gate is depleted by removing electrons from the floating gate so that it becomes positively charged. This causes the memory cell, a floating gate transistor, to have a lower threshold voltage. When the floating gate transistor has a low threshold voltage, the memory cell is conductive and recognized as a logic low. When the memory cell is unprogrammed (in the erased state), it has a higher threshold voltage and is characterized as having a high impedance which is recognized as a logic high. When the floating gate transistor will not stay programmed, it is because electrons leaked into the floating gate causing it to lose its charge. With the floating gate uncharged, the memory cell is a logic high.
It has been recognized, however, that all of the memory cells on a given integrated circuit chip do not have the same life expectancy with respect to the number of times they can be programmed and erased. This characteristic is known as endurance. There may be a relatively small number of memory cells which have low endurance. Once a single EEPROM cell begins failing due to losing its charge, the EEPROM is also failing even though a vast majority of the EEPROM cells are not losing their charge. One technique has been developed to compensate for a few weak cells causing the EEPROM as a whole to have low endurance. This technique provides two floating gate transistors at each memory cell location. For each access of a memory cell, two adjoining floating gate transistors are also accessed. The two adjoining floating gate transistors are connected in parallel. If one of the floating gate transistors cannot hold charge when programmed, perhaps the adjoining one will, thus extending the life of the EEPROM. This is effective because the failure mode is known to be to degrade to the high impedance state. If a memory location is programmed, conductivity is expected. Such conductivity will be provided if either floating gate transistor can hold its charge. If the logic low state is the desired state, even a faulty transistor will provide the desired high impedance. A faulty floating gate transistor provides the logic high state whether programmed or not programmed. Consequently, the endurance of the EEPROM is improved while not interfering with the desired functionality.